SenseICs architects, designs, and tests Integrated Circuits (ICs), printed circuit boards, and electronic systems.

We deliver turnkey IC solutions to commercial and defense high-level system integrators. We prioritize customer satisfaction through innovative design approaches challenging the status-quo. Our experience spans a wide range of imaging and RF applications with diverse fabrication nodes and processing technologies including 3DIC, BiCMOS, and advanced node FinFET.

Advanced Imaging

Read-Out Integrated Circuit (ROIC) designs endeavor to accommodate signals having a wide dynamic range. The key design challenge is to maintain ROIC sensitivity to low-light signal levels while simultaneously not clipping high level signals within a frame. This intra-frame dynamic range requirement often leads to making less-than-optimal global settings like frame gain, through a Programmable Gain Amplifier (PGA), or shutter time to preserve the integrity of the maximum signal acquired during a given frame exposure time. The global imaging settings allow for the utilization of the pixel maximum full-well capacity while compromising the integrity of dark signal levels. The new SenseICs High Dynamic Range (HDR) ROIC architecture utilizes a novel Intelligent Context Adaptive Sensing (ICAS) technology enabling not only intra-frame HDR but also reconfigurable frame-by-frame functions like auto exposure, Region of Interest (ROI) windowing, and event-driven, low-power imaging. The specialized front-end analog-digital technology enables a new generation of smart ROICs with on-the-fly adaptive reconfigurability and efficient image processing back-end.

Trusted Microelectronics

Guaranteeing the authenticity and trustworthiness of ICs used to assemble consumer or government systems is of the upmost importance. SenseICs is focused on enabling and developing ICs and systems to explore, analyze, detect, and secure vulnerabilities in the analog and mixed-signal domain. Relying on demonstrated capabilities in design, fabrication, and testing across a wide range of technologies including the 250 nm, 180nm, 90 nm, 130 nm, 65 nm, 45 nm, and 14nm nodes, SenseICs is currently delivering ICs and systems for hardware security R and D.

High Radiation Environments

Despite the trend of inherent enhanced total ionizing dose (TID) hardness of deep submicron CMOS technologies, TID effects remain a significant problem in IC design for space or nuclear applications. Additionally, transiting radiation causes single event effects (SEE) that disturb the operation of both analog and digital ICs at any process node. SenseICs is skilled in the process to mitigate these effects throughout the IC design cycle. Furthermore, SenseICs is versed in radiation effects testing and developing data acquisition systems for validating IC radiation tolerance and SEE immunity.

Secure 5G RFIC

Security of the 5G components used to assemble consumer or government wireless network infrastructures is critical to the growth of the US digital economy and to provide protection from cybersecurity threats. As a trusted technology vendor, SenseICs is focused on enabling and developing ICs and systems with assurance in mind to secure vulnerabilities in the future expansion of the 5G network. SenseICs goal is to develop trusted IP and turnkey RFIC to be deployed in secure 5G networks for IoT devices, autonomous vehicles, robotics, smart electricity grids, or sensitive government applications.


Ramy Tantawy is the Co-founder & CEO of SenseICs, an integrated circuit design company focused on revolutionizing imaging and RF sensors and systems. He is a Ph.D. Candidate in Electrical and Computer Engineering at The Ohio State University. He received his B.S. and M.E. (with distinction) degrees in Electrical Engineering from Northern Arizona University in 2001 and 2003, respectively. Prior to founding SenseICs, Mr. Tantawy spent over 15 years designing CMOS mixed-signal circuits in monolithic CMOS imagers, hybridized IR ROICs, and RF front-end transceivers. He authored and co-authored over 5 patents, and 12 conference and journal papers.

Dr. Shane Smith is the Co-founder and President of SenseICs and has more than 20 years of experience developing and maintaining electronic systems for integrated circuit research and high energy physics experiments. His work covers a range of activities including the design and development of radiation hard mixed signal ASICs, trusted microelectronics, FPGA based data acquisition systems, medical imaging electronics, chemical vapor deposition diamond detectors, and high voltage power supply systems. Dr. Smith is seasoned in EDA tool and PDK management with extensive successful tape-out experience in numorous advanced technology nodes.

Teddy Decker, CPA is the Finance & Accounting Manager of SenseICs. She earned her Bachelors of Business Administration with a concentration in accounting from the University of New Mexico. Ms. Decker has been a CPA since 1997 and has extensive experience in all areas of public accounting. She has specialized knowledge in the high-tech industry. Her previous work experience includes working for one of New Mexico’s most prestigious accounting firms where she provided high quality work in the audit & review, tax, information technology & forensic accounting departments.


Analog Design Engineer

The analog designer is expected to have experience/knowledge with circuit design at the transistor level in the Cadence environment from schematic entry to physical layout and parasitic extraction. Principle tasks will include:

  1. Design of analog blocks:
    bandgap, IDACs, VDACs, analog reference buffers, ADCs, switched capacitor circuits and amplifiers, SRAM, and IO/ESD design
  2. Top chip mixed-signal simulation
  3. Documenting designs for reviews and reports
  4. Test system design and fabricated chip characterization

Digital Design Engineer

The digital designer is expected to have experience/knowledge with circuit design digital flow from Cadence or Synopsys, and a working knowledge of analog design principles and signal / power integrity.

  1. Fluent in Verilog/VHDL
  2. Fluent in Cadence or equivalent Digital ASIC Tool Suite (Genus,Innovus,Tempus,Voltus)
  3. Experience with high-level design, simulation, and verification tools
  4. Experience with scripting languages Python/PERL